Several issues arise in the construction of power converters. The most problematic of these is the difficulty of creating noise-free output power without introducing noise into the input power. Conventional techniques directed toward this problem are well known, but complicated and expensive to implement. Conventional power converters introduce periodically varying components of the input current and can cause power loss. In addition, prior art power converters typically do not appear as a simple resistive load to the power input.
Prior art designs for boost converters for power factor correction (PFC), comprise two conventional approaches to the problem of minimizing ripple current. FIG. 5. illustrates a schematic diagram of a prior art power factor correction (PFC) boost converter 500. The two approaches for a system similar to that of FIG. 5 are discontinuous mode (DM) and continuous mode (CM).
In the converter 500 an alternating-current (AC) voltage supply VAC is coupled across input terminals of a full-wave bridge rectifier BR. A first output terminal of the bridge rectifier BR is coupled to a first terminal of an inductor L. A second terminal of the inductor L is coupled to a drain of a transistor switch M and to an anode of a diode D. A cathode of the diode D is coupled to a first terminal of an output capacitor C. A second output terminal of the bridge rectifier BR is coupled to a first terminal of a sensing resistor RSENSE. A second terminal of the sensing resistor RSENSE, a source of the transistor switch M and a second terminal of the capacitor C are each coupled to a ground node. A voltage signal −ISENSE formed at the first terminal of the sensing resistor RSENSE is representative of current drawn by the boost converter 500 from the supply VAC. The signal −ISENSE is negative in polarity because it is formed by a voltage drop across the resistor RSENSE referenced to ground. A switch control voltage signal VSW is applied to the gate of the transistor switch M and controls whether the transistor switch M is conductive (switch closed) or non-conductive (switch open).
When the switch M is closed, a current flows from the bridge rectifier BR through the inductor L and through the switch M. Under such conditions, the diode D is reverse-biased by the output voltage VOUT. Current flowing through the inductor L stores energy as a magnetic field associated with the inductor L. When the switch M is opened, the stored energy is transferred to the output capacitor C by a current which flows through the diode D. Under such conditions, the diode D is forward-biased. The energy stored in the output capacitor C forms the output voltage VOUT across the capacitor C which is available for driving a load, such as a second power supply stage. A rate of energy transfer from the source VAC to the capacitor C depends upon a duty cycle of the switch control signal VSW.
The boost converter 500 illustrated in FIG. 5 controls the times at which switching of the transistor switch M occurs such that the current draws from the alternating-current supply VAC by the boost converter 500 is substantially in phase with the voltage provided by the supply VAC and to control the duty cycle of the transistor switch M such that the output voltage VOUT is maintained at a constant level. The voltage VOUT and the voltage −ISENSE are both monitored for controlling switching.
When such a boost converter 500 is operated in CM, the current flowing through the inductor L remains above zero at all times. Thus, at the instant of closure of the switch M, current is flowing through the diode D. Energy stored in the junction associated with the diode D results in a finite recovery time for the diode D such that the diode D does not turn off instantaneously. Rather, energy stored in the junction of the diode D is discharged through the switch M upon its closure. A resulting high level of current in the switch M can cause excessive power dissipation and premature failure of the switch M. Because this high level of current occurs each time the switch M is cycled, the switching frequency is limited. This is especially true for boost converters which drive a second power supply stage because such boost converters typically generate a regulated voltage of approximately 400 volts across the output capacitor C. Further, because the PFC boost converter 500 controls the times at which switching occurs such that the voltage and current provided by the supply VAC are in phase with each other, this problem of elevated current in the switch M cannot conventionally be avoided by allowing the current in the diode D to fall to zero prior to closing the switch M as would occur if the converter 500 were operated DM.
When operating in DM, the converter 500 typically exaggerates the ripple allowing the current through L to drop to a minimum of zero, while simultaneously raising the maximum current value. This extension of the range of allowed current values for DM converters means the average value of the current in L remains constant regardless of the mode of operation. While this preservation of current allows a converter to attain both less lossy switching and improved efficiency over a CM converter, it unfortunately introduces high ripple into both input and output current.
Prior art systems have attempted to reduce the ripple effects by using multiple converters of the above design, modifying their relative phases, and combining their output power. The phase of each converter is modified relative to the other converters such that the ripple components of the converters cancel one another out. Such a device is illustrated in FIG. 6.
It is known to cancel the input ripple current drawn by a system in order to power a load. It is known in the art to effect input ripple current cancellation by coupling two power sources in parallel and by providing the two power sources with switching frequencies that are 180° out of phase. The prior art system 20 illustrated in FIG. 6 provides for the cancellation of input ripple current in this manner. The system 20 includes a first boost-type power converter 21 (a first power source), which comprises a PWM controller 22, a FET power switch M1, an inductance L1, a rectifier D1, and a filter capacitor C1. The power converter 21 operates in a manner that is well-known, and will not be described further herein. The power supplied to the load 26 by the first power converter 21 is regulated by the feedback network 27 and the PWM controller 22, the output of which is coupled to the gate electrode of the FET power switch M1. A voltage divider formed by the resistors R3 and R4 of feedback network 27 divides the output voltage of the first power converter 21 and compares the divided output voltage against a reference voltage VREF3 in the amplifier U6. The output voltage from the amplifier U6 is then coupled to the control input of the PWM controller 22 to regulate the ON time of the power switch M1.
The system 20 further includes a second boost-type power converter 23 (a second power source), which comprises a PWM controller 24, a FET power switch M2, an inductance L2, a rectifier D2, and a filter capacitor C2. The power converter 23 operates in a manner that is well-known, and will not be described further herein. The power supplied to the load 26 by the second power converter 23 is also regulated by the feedback network 27 and by the PWM controller 24, the output of which is coupled to the gate electrode of the FET power switch M2. The output voltage from the amplifier U6 is also coupled to the control input of the PWM controller 24 to regulate the ON time of the power switch M2.
As is well-known, the currents flowing through the inductors L1 and L2 in the power converters 21 and 23 respectively have triangular waveforms. A fixed-frequency oscillator 25 is directly coupled to the clock input of the PWM controller 22 and is coupled to the clock input of the PWM controller 24 through the inverter N2 to provide the PWM controllers 22 and 24 with clock waveforms that are 180° out of phase. As a result, the triangular current waveforms for the inductors L1 and L2 will be 180° out of phase. Therefore, the triangular component of the input current is cancelled, leaving only the DC component of the input current. The circuit of FIG. 6 does not address the problem of current or power equalization to the load 26. Further, since the components of the two power sources are not identical, slight phase differences naturally occur. Resulting in a ripple current large enough to prevent application of this circuit to a high power device.
It is known to combine variable frequency power sources for supplying power to a load, and to further use phase detection to equalize the currents supplied to a load by each of the power sources, and to cancel a ripple component of the input current drawn by the system.
FIG. 7 shows a block diagram that illustrates a system 30 for supplying power to the load 36. The system 30 includes first and second power sources 31 and 32 which are coupled together at their input terminals and supply power to the same load 36. Each of the power sources 31 and 32 is a variable-frequency power source that has a relationship between its switching frequency and the power that it supplies to a load. For example, each power source 31 and 32 can have a relationship between its switching frequency and the power that it supplies to a load that is either linear or non-linear. At the same time, each power supply can also have a relationship between its switching frequency and the power that it supplies to the load that is direct, so that power and switching frequency increase or decrease in the same direction, or inverse, so that power and switching frequency change in opposite directions. The power sources 31 and 32 of the system 30 have similar relationships between their switching frequencies and the power that they supply to the load 36. The first and second power sources 31 and 32 can be coupled to one another in parallel, as shown in FIG. 7.
Referring to FIG. 7, the system further includes feedback networks 33 and 34 associated with, respectively, the first and second power sources 31 and 32. The first feedback network 33 couples a portion of the output voltage of the first power source 31 to a control terminal CTRL of the first power source 31 to vary the first switching frequency fsw1 of the first power source 31, thereby regulating the power supplied by the first power source 31 to the load 36. Similarly, the second feedback network 34 couples a portion of the output voltage of the second power source 32 to a control terminal CTRL of the second power source 32 to vary the second switching frequency fsw2 of the second power source 32, thereby regulating the power supplied by the second power source 32 to the load 36.
The phase detection means 35 provides an error signal that is representative of the difference in phase between the first switching frequency fsw1 of the first power source 31 and the second switching frequency fsw2 of the second power source 32. The first switching frequency fsw1 is coupled from a terminal of the first power source 31 and is applied to an input terminal of the phase detection means 35. Similarly, the second switching frequency fsw2 is coupled from a terminal of the second power source 32 and is applied to the other input terminal of the phase detection means 35. The error signal provided by the phase detection means 35 is coupled to the feedback networks 33 and 34. The result is that the first and second switching frequencies fsw1 and fsw2 are locked to one another.
Furthermore, because the first and second power sources 31 and 32 have similar relationships between their switching frequencies and the power that they supply to a load, the power supplied to the load 36 by the first power source 31 is substantially equal to the power supplied to the load 36 by the second power source 32. In FIG. 7, the substantial equalization of the power supplied to the load 36 by the first and second power sources 31 and 32 means that the currents supplied to the load 36 by each of the power sources 31 and 32 are substantially equalized, because the power sources 31 and 32 are coupled to one another in parallel and, thus, apply the same voltage to the load 36.
The circuit of FIG. 7 utilizes a loop which is designed to lock the relative phase of the two power sources at 180° apart. Unfortunately, because the duty cycles of the two power sources are not always 50%, the phases are not always fully opposite. Furthermore, the device of FIG. 7 loses phase lock at the limits of the regulation loop, which results in a complete loss of input ripple current cancellation, and can result in audible noise emanating from the device.